1. Field of the Invention
This invention relates to a liquid crystal display. More particularly, the invention relates to a method of driving a liquid crystal display that eliminates stripe-shaped noise when a picture is displayed on an enlarged area.
2. Description of the Related Art
A liquid crystal display (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to display a picture. The LCD may be an active matrix type having a switching device for each cell and used in a display device, such as a monitor for a computer, office equipment, a cellular phone and the like. The switching device for the active matrix LCD mainly employs a thin film transistor (TFT).
FIG. 1 schematically shows a related art LCD driving apparatus.
Referring to FIG. 1, the related art LCD driving apparatus includes a liquid crystal display panel 2 having m×n liquid crystal cells Clc arranged in a matrix, m data lines D1 to Dm and n gate lines G1 to Gn crossing each other and thin film transistors TFT located at the crossings of the data and gate lines, a data driver 4 for applying data signals to the data lines D1 to Dm of the liquid crystal display panel 2, a gate driver 6 for applying scanning signals to the gate lines G1 to Gn, a gamma voltage supplier 8 for supplying the data driver 4 with gamma voltages, and a timing controller 10 for controlling the data driver 4 and the gate driver 6.
The liquid crystal display panel 2 further includes a plurality of liquid crystal cells Clc arranged, in a matrix, at the intersections between the data lines D1 to Dm and the gate lines G1 to Gn. The thin film transistor TFT provided at the intersections for each liquid crystal cell Clc applies a data signal from each data line D1 to Dm to the liquid crystal cell Clc in response to a scanning signal from the gate line G. Further, each liquid crystal cell Clc includes a storage capacitor Cst. The storage capacitor Cst is provided between a pixel electrode of the liquid crystal cell Clc and a pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line to maintain a constant voltage of the liquid crystal cell Clc.
The gamma voltage supplier 8 applies a plurality of gamma voltages to the data driver 4 such that an analog data signal is generated.
The timing controller 10 generates a gate control signal GCS and a data control signal DCS using synchronizing signals (or a complex synchronizing signal) supplied from another system (not shown). Herein, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The data control signal DCS includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity signal POL. The timing controller 10 re-aligns the R, G and B data to apply them to the data driver 4.
The data driver 4 applies pixel signals for each line for every horizontal period in response to the data control signal DCS from the timing controller 10 to the data lines D1 to Dm. Particularly, the data driver 4 converts digital R, G and B data from the timing controller 10 into analog pixel signals using gamma voltages from the gamma voltage supplier 8 to apply them to the data lines D1 to Dm.
More specifically, the data driver 4 shifts a source start pulse SSP in response to a source shift clock SSC to generate sampling signals. Then, the data driver 4 sequentially receives the R, G and B data for a certain unit in response to the sampling signals to latch them. Further, the data driver 4 converts the latched R, G and B data for one line into analog data signals to apply them to the data lines D1 to Dm in an enable interval of the source output enable signal SOE. Herein, the data driver 4 converts the data signals into positive signals or negative signals in response to a polarity control signal POL.
The gate driver 6 sequentially applies a scanning signal (or a gate high voltage) to the gate lines G1 to Gn in response to the gate control signal GCS from the timing controller 10. Thus, the thin film transistors TFT connected to the gate lines G1 to Gn are sequentially driven.
To this end, the gate driver 6 includes a plurality of gate integrated circuits 12, each of which is configured as shown in FIG. 2 schematically. Referring to FIG. 2, the gate integrated circuit 12 include a shift register block 14, a level shifter 18 and an output buffer 20.
The shift register block 14 consists of i shift registers 16 and 17 (wherein i is an integer). Such a shift register block 14 sequentially generates a shift pulse. The level shifter 18 generates a scanning signal using a shift pulse applied thereto. The output buffer 20 applies the scanning signal from the level shifter 18 to the corresponding gate line G.
Operation of the gate integrated circuit 12 will be described in detail with reference to FIG. 3.
First, the shift register block 14 receives the gate start pulse GSP signal and the gate shift clock GSC signal from the timing controller 10. The gate shift clock GSC has a period of one horizontal period 1H. The shift register block 14 having received the gate start pulse GSP and the gate shift clock GSC shifts the gate start pulse GSP from the 1st shift register 16 to the ith shift register 17 for each period of the gate shift clock GSC. Whenever the gate start pulse GSP is shifted to the adjacent shift register (i.e., every one horizontal period 1H), a shift pulse is generated from the corresponding shift register that is applied to the level shifter 18.
The level shifter 18 receives a gate output enable signal GOE from the timing controller 10. The gate output enable signal GOE is applied, via an inverter (not shown), to the level shifter 18. The level shifter 18 having received the shift pulse for each horizontal period 1H generates a scanning pulse corresponding to the shift pulse in a high interval (or a low interval upon going through the inverter) of the gate output enable signal GOE to apply the signal to the output buffer 20. The output buffer 20 sequentially applies the scanning signal supplied thereto to the gate lines G to sequentially drive the gate lines G.
In the related art as mentioned above, a desired picture is displayed on the liquid crystal display panel 2 that correspond to data signals and scanning signals from the data driver 4 and the gate driver 6. Recently, as various media have become available, image data having various formats have been used. When data having a specific format (e.g., a DVD format) is directly displayed on the display panel, as depicted in FIG. 4, the top portion 22 and the bottom portion 24 of the panel are displayed in a specific pattern (e.g., a black color). In other words, only a portion excluding the top portion 22 and the bottom portion 24 is used as an effective display part.
Accordingly, various schemes are necessary to use the entire panel, including the top portion 22 and the bottom portion 24 of the panel, as the effective display part. For example, data for one line is applied to two lines as shown in FIG. 5 to expand the effective display part. More specifically, first, the LCD supplies the same data for a given line unit (e.g., for a three line unit). In other words, data for the kth gate line Gk (wherein k is 1, 4, 7, 10 . . . ) and for the (k+1)th gate line Gk+1 is supplied with no change from the initial data, whereas data for the (k+2)th gate line Gk+2 are supplied two lines by two lines to expand the picture screen. In other words, as shown in FIG. 5, data for the first and second gate lines G1 and G2 is supplied with no change, while data for the third gate line G3 is supplied to the third and fourth gate lines G3 and G4 to obtain an expanded effective display part like the right screen of FIG. 4.
To this end, a period of the gate shift clock GSC is changed to a ½ horizontal period in a given line unit as shown in FIG. 6. The gate shift clock GSC having the normal period allows a scanning signal having about one horizontal period to be applied to the first and second gate lines G1 and G2, whereas the gate shift clock GSC having a period of ½ horizontal period allows a scanning signal having about ½ horizontal period to be applied to the third and fourth gate lines G3 and G4. Herein, the third and fourth gate lines G3 and G4 are supplied with the same data D3, thereby expanding the picture field.
However, such a related art field expansion method has a problem in that noise is generated for each line. Furthermore, because a period of the scanning signal applied to the third and fourth gate lines G3 and G4 is different from periods of other scanning signals, a reduced picture quality for each line occurs at a particular area of the liquid crystal display panel 2.